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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-11411-2E
MEMORY
CMOS
2 x 1 M x 32-BIT SINGLE DATA RATE I/F FCRAMTM
Consumer/Embedded Application Specific Memory for SiP
MB81ES653225-12/-12L
CMOS 2-Bank x 1,048,576-Word x 32-Bit Fast Cycle Random Access Memory (FCRAM) with Single Data Rate for SiP DESCRIPTION
The Fujitsu MB81ES653225 is a Single Data Rate Interface Fast Cycle Random Access Memory (FCRAM*) containing 67,108,864 memory cells accessible in a 32-bit format. The MB81ES653225 features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. The MB81ES653225 is utilized using a Fujitsu advanced FCRAM core technology and designed for low power consumption and low voltage operation than regular synchronous DRAM (SDRAM) . The MB81ES653225 is dedicated for SiP (System in a package) , and ideally suited for various embedded/ consumer applications including digital AVs and image processing where a large band width and low power consumption memory is needed. * : FCRAM is a trademark of Fujitsu Limited, Japan.
PRODUCT LINE
Parameter Clock Frequency (Max) Burst Mode Cycle Time (Min) Access Time from Clock (Max) Operating Current (Max) (32 page length) Power Down Mode Current (Max) Self Refresh Current (Max) (Ta = +85 C) 0.5 mA 1000 A CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 MB81ES653225 12 54.0 MHz 85.0 MHz 18.5 ns 11.7 ns 12 ns 8.7 ns 35 mA 0.1 mA 450 A 12L
MB81ES653225-12/-12L
FEATURES
* 1 M word x 32 bit x 2 banks organization * Low power supply - VDD : + 1.8 V 0.15 V - VDDQ : + 1.8 V 0.15 V * 1.8 V-CMOS I/O interface * 8 K refresh cycles every 32 ms * Auto-and Self-refresh * Two banks operation * Burst read/write operation and burst read/single write operation capability * Programmable burst type, burst length, and CAS Latency * Programmable page length function * Programmable Partial Array Self Refresh (PASR) * Programmable Temperature Compensated Self Refresh (TCSR) * Deep power down mode * Extended temperature operation - MB81ES653225-12 : From 0 C to +85 C (Ta) - MB81ES653225-12L : From -25 C to +85 C (Ta) * CKE power down mode * Output enable and input data mask * Disable function for TEST * Self burnin function for TEST * Built In Self Test (BIST) function for TEST
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PAD LAYOUT
VDD VSS A9 A12 A13 TBST A14 BME DQM1 DQM3 VDDQ DSE VSSQ DQ8 DQ9 DQ10 DQ11 VDDQ VSSQ DQ12 DQ13 DQ14 DQ15 DQ24 DQ25 DQ26 DQ27 VDDQ VSSQ DQ28 DQ29 DQ30 DQ31 VDD VSS VDD VSS CKE CLK CSB RASB CASB WEB BA A11 A10 A0 A1 A2 A3 A4 A5 A6 A7 A8 DQM0 DQM2 VDDQ VSSQ DQ0 DQ1 DQ2 DQ3 VDDQ VSSQ DQ4 DQ5 DQ6 DQ7 DQ16 DQ17 DQ18 DQ19 VDDQ VSSQ DQ20 DQ21 DQ22 DQ23 VDD VSS
Pad No. 137
Pad No. 1
Pad No. 72
Pad No. 71
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PAD DESCRIPTIONS
Symbol VDDQ, VDD DQ31 to DQ0 VSSQ, VSS WE (WEB) CAS (CASB) RAS (RASB) CS (CSB) BA AP Supply Voltage Data I/O Ground Write Enable Column Address Strobe Row Address Strobe Chip Select Bank Select (Bank Address) Auto Precharge Enable Row A14 to A0 * Address Input 128 page 64 page 32 page CKE CLK DQM3 to DQM0 DSE BME TBST Clock Enable Clock Input Input Mask/Output Enable Disable Mode Entry (apply VSS except Disable Mode) Self Burn-in Mode Entry (apply VSS except Self Burn-in Mode) BIST Mode Entry (apply VSS except BIST Mode) Don't Bond A12 to A0 A13 to A0 A14 to A0 Column A6 to A0 A5 to A0 A4 to A0 Function
* : A13 must be connected to VSS in 128 page length mode. A14 must be connected to VSS in 128 page length mode and 64 page length mode.
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BLOCK DIAGRAM
CLK
To each block CLOCK BUFFER
CKE
BANK-1 BANK-0
RAS
CS RAS CAS WE DSE BME TBST
CONTROL SIGNAL LATCH COMMAND DECODER
CAS
WE
MODE REGISTER
FCRAM CORE (1,048,576 x 32) ROW ADDRESS
A9 to A0, A10/AP, A14 to A11
BA
ADDRESS BUFFER/ REGISTER
COL. ADDRESS COLUMN ADDRESS COUNTER
I/O
DQM3 to DQM0 DQ31 to DQ0
I/O DATA BUFFER/ REGISTER
VDDQ VDD VSS VSSQ
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MB81ES653225-12/-12L
FUNCTIONAL TRUTH TABLE *1
1. COMMAND TRUTH TABLE *2, *3, *4
Function Device Deselect *5 No Operation * Burst Stop * * Read *7 Read with Auto-precharge *7 Write *
7 7 5 6, 7
Symbol DESL NOP BST READ READA WRIT WRITA ACTV PRE PALL MRS
CKE n-1 H H H H H H H H H H H n X X X X X X X X X X X
CS H L L L L L L L L L L
RAS CAS WE X H H H H H H L L L L X H H L L L L H H H L X H L H H L L H L L L
BA X X X V V V V V V X V
A10 (AP) X X X L H L H L H V
Address (Except for A10) X X X Column Address Column Address Column Address Column Address Row Address X X V
Write with Auto-precharge * Bank Active *8 Precharge Single Bank Precharge All Banks Mode Register Set * *
9, 10
*1 : V = Valid, L = Logic Low, H = Logic High, X = either L or H. Row Address 128 page length : A12 to A0 64 page length : A13 to A0 32 page length : A14 to A0 Column Address 128 page length : A6 to A0 64 page length : A5 to A0 32 page length : A4 to A0 *2 : All commands assume no CSUS command on previous rising edge of clock. *3 : All commands are assumed to be valid state transitions. *4 : All inputs are latched on the rising edge of clock. *5 : NOP and DESL commands have the same effect. Unless specifically noted, NOP will represent both NOP and DESL command in later description. *6 : When the current state is idle and CKE = L, BST command will represent Deep Power Down command. Refer to "3. CKE TRUTH TABLE" in section "FUNCTION TRUTH TABLE". *7 : READ, READA, WRIT, WRITA and BST commands should only be issued after the corresponding bank has been activated (ACTV command) . Refer to "STATE DIAGRAM". *8 : ACTV command should only be issued after corresponding bank has been precharged (PRE or PALL command) . *9 : Required after power up. Refer to "22. POWER-UP INITIALIZATION" in section "FUNCTIONAL DESCRIPTION". *10 : MRS command should only be issued after all banks have been precharged (PRE or PALL command) . Refer to "STATE DIAGRAM".
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2. DQM TRUTH TABLE
Function Data Write/Output Enable Data Mask/Output Disable *1 : i = 0, 1, 2, 3 *2 : DQM0 for DQ7 to DQ0, DQM1 for DQ15 to DQ8, DQM2 for DQ23 to DQ16, DQM3 for DQ31 to DQ24 Symbol ENBi *1 MASKi *1 CKE n-1 H H n X X DQMi *1, *2 L H
3. CKE TRUTH TABLE *1
CKE Current State Bank Active Any (Except Idle) Clock Suspend Idle Idle Self Refresh Idle Power Down Idle Deep Power Down Function Clock Suspend Mode Entry *2 Clock Suspend Continue *2 Clock Suspend Mode Exit Auto-refresh Command *3 Self-refresh Entry *3, *4 Self-refresh Exit *5 Power Down Entry *3, *4 Power Down Exit Deep Power Down Entry *3, *4 Deep Power Down Exit Command CSUS REF SELF SELFX PD PDX DPD DPDX n-1 H L L H H L L H H L L H L L n L L H H L H H L L H H L H H CS X X X L L L H L H L H L L H RAS CAS WE X X X L L H X H X H X H H X X X X L L H X H X H X H H X X X X H H H X H X H X L H X BA X X X X X X X X X X X X X X A10 (AP) X X X X X X X X X X X X X X Address (Except for A10) X X X X X X X X X X X X X X
*1 : Address : A12 to A0 @128 page length mode : A13 to A0 @64 page length mode : A14 to A0 @32 page length mode *2 : The CSUS command requires that at least one bank is active. Refer to "STATE DIAGRAM". *3 : REF, SELF, DP and DPD commands should only be issued after all banks have been precharged (PRE or PALL command) . Refer to "STATE DIAGRAM". *4 : SELF, PD and DPD commands should only be issued after the last read data have been appeared on DQ. *5 : CKE should be held high within one tRC period after tCKSP .
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4. OPERATION COMMAND TABLE (single bank operation) *1
Current State CS H L L L Idle L L L L L H L L L Bank Active L L L L L H L L L Read L L L L L RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X H L H L H L H L X H L H L H L H L X H L H L H L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL NOP BST READ/READA Begin Read; Determine AP WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS Begin Write; Determine AP Illegal *2 Precharge; Determine Precharge Type Illegal NOP (Continue Burst to End Bank Active) Burst Stop Bank Active Terminate Burst, New Read; Determine AP Terminate Burst, Start Write; Determine AP *4 Illegal *2 Terminate Burst, Precharge Idle Illegal (Continued) NOP Illegal *2 Bank Active after tRCD NOP *5 Auto-refresh or Self-refresh *3, *6 Mode Register Set (Idle after tRSC) *3, *7 NOP Function
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Current State
CS H L L L
RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L
CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L
WE X H L H L H L H L X H L H L H L H L X H L H L H L H L
Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE
Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS Illegal Illegal *2 Illegal Illegal *2
Function NOP (Continue Burst to End Bank Active) Burst Stop Bank Active Terminate Burst, Start Read; Determine AP *4 Terminate Burst, New Write; Determine AP Illegal *2 Terminate Burst, Precharge Idle Illegal NOP (Continue Burst to End Precharge Idle) Illegal
Write
L L L L L H L L L L L L L L H L L L L L L L L
Read with Autoprecharge
NOP (Continue Burst to End Precharge Idle) Illegal
Write with Autoprecharge
(Continued)
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MB81ES653225-12/-12L
(Continued) Current State
CS H L L L L L L L L H L L L
RAS X H H H H L L L L X H H H H L L L L X H H L L X H H H
CAS X H H L L H H L L X H H L L H H L L X H L H L X H H L
WE X H L H L H L H L X H L H L H L H L X X X X X X H L X
Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X MODE X X X X X X X X X
Command DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACTV PRE/PALL REF/SELF MRS DESL NOP/BST READ/READA/ WRIT/WRITA ACTV/ PRE/PALL REF/SELF/ MRS DESL NOP BST READ/READA/ WRIT/WRITA ACTV/PRE/ PALL/REF/ SELF/MRS Illegal Illegal Illegal *2 Illegal *2
Function NOP (Idle after tRP) NOP (Idle after tRP) *8
Precharging
NOP (PALL may affect other bank) *5 Illegal
NOP (Bank Active after tRCD)
Bank Activating
L L L L L H L L
NOP (Idle after tRC) NOP (Idle after tRC) *8
Refreshing L L H L Mode Register Setting L L
NOP (Idle after tRSC)
Illegal
L
L
X
X
X
RA = Row Address BA = Bank Address CA = Column Address AP = Auto Precharge 10
MB81ES653225-12/-12L
*1 : All command entries assume the CKE was High during the proceeding clock cycle and the current clock cycle. After illegal commands are asserted, following command function and data could not be guaranteed. If used, power up sequence be asserted after power shout down. *2 : Illegal to bank in the specified state; entry may be legal in the bank specified by BA, depending on the state of that bank. *3 : Illegal if any bank is not idle. *4 : Must satisfy bus contention, bus turn around, and/or write recovery requirements. Refer to "11. READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4) " and "12. WRITE TO READ TIMING (EXAMPLE @ CL = 2, BL = 4) " in section "TIMING DIAGRAMS". *5 : NOP to bank precharging or in idle state. May precharge bank specified by BA (and AP) . *6 : SELF command should only be issued after the last read data have been appeared on DQ. *7 : MRS command should only be issued on condition that all DQ are in Hi-Z. *8 : BST command should only be issued with CKE = "H".
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5. COMMAND TRUTH TABLE FOR CKE *1
Current State CKE n-1 H L L Selfrefresh L L L L L H H Selfrefresh Recovery H H H H H H L Power Down L L L L H L Deep Power Down L L L L CKE n X H H H H H L X H H H H H H L X H H L H H X H H L H H CS X H L L L L X X H L L L L X X X H L X L L X H L X L L RAS X X H H H L X X X H H H L X X X X H X L H X X H X L H CAS X X H H L X X X X H H L X X X X X H X X L X X H X X L WE X X H L X X X X X H L X X X X X X H X X X X X H X X X Address X X X X X X X X X X X X X X X X X X X X X X X X X X X Illegal *2 Invalid Exit Power Down Mode Idle NOP (Maintain Power Down Mode) Illegal Invalid Exit Deep Power Down Mode Idle *3 NOP (Maintain Deep Power Down Mode) Illegal (Continued) Illegal NOP (Maintain Self-refresh) Invalid Idle after tRC Illegal Invalid Exit Self-refresh (Self-refresh Recovery Idle after tRC) Function
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(Continued) Current State CKE n-1 H Bank Active Bank Activating Read/Write All Banks Idle CKE n H CS X RAS X CAS X WE X Address X Function Refer to "4. Operation Command Table". Refer to "4. Operation Command table". Start Clock Suspend next cycle Invalid Refer to "4. Operation Command Table". Illegal
H
L
X
X
X
X
X
L H H Precharging Refreshing H H H H L H Clock Suspend L L L Any State Other Than Listed Above H H
X H L L L L L X X H L X H L
X X L H L L L X X X X X X X
X X H X L H H X X X X X X X
X X H X X L H X X X X X X X
X X L X X X H X X X X X X X
X X X X X X X X X X X X X X
Refer to "4. Operation Command Table".
Invalid Invalid Exit Clock Suspend next cycle Maintain Clock Suspend Invalid Refer to "4. Operation Command Table". Illegal
*1 : All entries are specified at CKE (n) state. CKE input must satisfy corresponding set up and hold time for CKE. . *2 : CKE should be held High for tRC period after tCKSP *3 : After deep power down exit, it requires "19. DEEP POWER DOWN EXIT TIMINIG" procedure in section "TIMING DIAGRAMS".
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FUNCTIONAL DESCRIPTION
1. SDR I/F FCRAM BASIC FUNCTION
Three major differences between this SDR I/F FCRAMs and conventional DRAMs are : synchronized operation, burst mode, and mode register. The synchronized operation is the fundamental difference. An SDR I/F FCRAM uses a clock input for the synchronization, where the DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each operation of DRAM is determined by their timing phase differences while each operation of SDR I/F FCRAM is determined by commands and all operations are referenced to a positive clock edge. The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column addresses for the first access is set, following addresses are automatically generated by the internal column address counter. The mode register is to justify the SDR I/F FCRAM operation and function into desired system conditions. Refer to "MODE REGISTER TABLE".
2. FCRAMTM
The MB81ES653225 utilizes FCRAM core technology. The FCRAM is an acronym of Fast Cycle Random Access Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
3. CLOCK INPUT (CLK) and CLOCK ENABLE (CKE)
All input and output signals of SDR I/F FCRAM use register type buffers. A CLK is used as a trigger for the register and internal burst counter increment. All inputs are latched by a positive edge of CLK. All outputs are validated by the CLK. CKE is a high active clock enable signal. When CKE = Low is latched at a clock input during active cycle, the next clock will be internally masked. During idle state (all banks have been precharged) , the Power Down mode (standby) is entered with CKE = Low and this will make low standby current. The standby current of the Deep Power Down mode is lower than that of the Power Down mode. This mode is entered with CKE = Low, RAS = CAS = High and WE = Low.
4. CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, command signals are negated but internal operation such as burst cycle will not be suspended. If such a control isn't needed, CS can be tied to ground level.
5. COMMAND INPUT (RAS, CAS and WE)
Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDR I/F FCRAM operation, such as Row address strobe by RAS. Instead, each combination of RAS, CAS, and WE input in conjunction with CS input at a rising edge of the CLK determines SDR I/F FCRAM operation. Refer to "1. COMMAND TRUTH TABLE" in section "FUNCTIONAL TRUTH TABLE."
6. ADDRESS INPUT (A14 to A0)
Address input selects an arbitrary location of a total of 1,048,576 words of each memory cell matrix. Address field is defined for selected page length by the Programmable Page Length mode : 128 page length = A12 to A0, 64 page length = A13 to A0, 32 page length = A14 to A0. A total of twenty address input signals are required to decode such a matrix. SDR I/F FCRAM adopts an address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV) , Row addresses are initially latched and the remainder of Column addresses are then latched by a Column address strobe command of either a Read command (READ or READA) or Write command (WRIT or WRITA) .
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7. BANK SELECT (BA)
This SDR I/F FCRAM has two banks in one part and each bank is organized as 1 Mwords by 32-bit. Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA) , write (WRIT or WRITA) , and precharge command (PRE) .
8. DATA INPUT AND OUTPUT (DQ31 to DQ0)
Input data is latched and written into the memory at the clock following the write command input. Data output is obtained by the following conditions followed by a read command input : tRAC; from the bank active command when tRCD (Min) is satisfied. (This parameter is reference only.) tCAC; from the read command when tRCD is greater than tRCD (Min) . (This parameter is reference only.) tAC ; from the clock edge after tRAC and tCAC. The polarity of the output data is identical to that of the input. Data is valid between access time (determined by the three conditions above) and the next positive clock edge (tOH) .
9. DATA I/O MASK (DQM)
DQM is an active high enable input and has an output disable and input mask function. During burst cycle and when DQM0 to DQM3 = High is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. DQM0, DQM1, DQM2, DQM3, controls DQ7 to DQ0, DQ15 to DQ8, DQ23 to DQ16, DQ31 to DQ24, respectively.
10. BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access. The burst mode is implemented by keeping the same row address and by automatic strobing column address. Access time and cycle time of burst mode is specified as tAC and tCK, respectively. The internal column address counter operation is determined by a mode register which defines burst type and burst count length of 1, 2, 4 or 8 bits of boundary or full column. In order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required. Current Stage Burst Read Burst Read Burst Write Burst Write Burst Read Burst Write Next Stage Burst Read Burst Write Burst Write Burst Read Precharge Precharge 1st Step 2nd Step Method (Assert the following command) Read Command Mask Command (Normally 3 clock cycles) Write Command after lOWD Write Command Read Command Precharge Command Precharge Command
The burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. The sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns + 1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least significant address ( = 0) . The interleave mode is a scrambled decoding scheme for A2 and A0. If the first access of column address is even (0) , the next address will be odd (1) , or vice-versa. When the full column burst operation is executed at single write mode, Auto-precharge command is valid only at write operation.
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Starting Column Address A2 A1 A0 XX0 XX1 X00 4 X01 X10 X11 000 001 010 8 011 100 101 110 111
Burst Length 2
Sequential Mode 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
Interleave Mode 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
11. FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full column burst mode is repeatedly access to the same row. If burst mode reaches the end of column address, then it wraps around to the first column address ( = 0) and continues to count until interrupted by the new read (READ) /write (WRIT) , precharge (PRE) , or burst stop (BST) commands. The selection of Auto-precharge option is illegal during the full column burst operation. The BST command is applicable to terminate the burst operation. If the BST command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to Bank Active. When a read mode is interrupted by the BST command, the output will be in High-Z. For the detailed rule, please refer to "8. READ INTERRUPTED BY BURST STOP (EXAMPLE @CL = 2, BL = Full Column" in section "TIMING DIAGRAMS". When a write mode is interrupted by the BST command, the data to be applied at the same time with the BST command will be ignored.
12. BURST READ & SINGLE WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this mode, burst read operation does not be affected by this mode.
13. PROGRAMMABLE PAGE LENGTH FUNCTION
The programmable page length function provides lower operation current than regular SDRAM. Page length is selected by Mode Register Set, and row address field and column address field are defined for selected page length as below. Row address A12 to A0 A13 to A0 A14 to A0 Column address A6 to A0 A5 to A0 A4 to A0
128 page length 64 page length 32 page length 16
MB81ES653225-12/-12L
Row/column address allocation at each page length is shown as the following table. For example, A14 (row address) at 32 page length mode is corresponded to A5 (column address) at 64 page length mode. Row : A14 to A0 0 0 0 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 8 8 8 9 9 9 10 10 10 11 11 11 12 12 12 13 13 6 14 5 5 4 4 4 Row : A13 to A0 Row : A12 to A0 Column : A4 to A0 3 3 3 2 2 2 1 1 1 0 0 0 Column : A0 to A5 Column : A6 to A0
32 page 64 page 128 page
14. PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
SDR I/F FCRAM memory core is the same as conventional DRAMs', requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is executed by the Precharge command (PRE) . With the Precharge command, SDR I/F FCRAM will automatically be in standby state after precharge time (tRP) . The precharged bank is selected by combination of AP and BA when Precharge command is asserted. If AP = High, all banks are precharged regardless of BA (PALL) . If AP = Low, a bank to be selected by BA is precharged (PRE) . The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command assertion. This auto precharge is entered by AP = High when a read or write command is asserted. Refer to "1. COMMAND TRUTH TABLE" in section "FUNCTIONAL TRUTH TABLE".
15. AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The SDR I/F FCRAM Auto-refresh command (REF) generates Precharge command internally. All banks of SDR I/F FCRAM should be precharged prior to the Autorefresh command. The Auto-refresh command should also be asserted every 3.9 s or a total 8192 refresh commands within 32 ms period.
16. SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue the refresh function until cancelled by SELFX. The Self-refresh is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF) . Once SDR I/F FCRAM enters the self-refresh mode, all inputs except for CKE will be "don't care" (either logic high or low level state) and outputs will be in a High-Z state. During a self-refresh mode, CKE = Low should be maintained. SELF command should only be issued after last read data has been appeared on DQ Note : When the burst refresh method is used, a total of 8,192 auto-refresh commands within 2 ms must be asserted prior to the self-refresh mode entry.
17. SELF-REFRESH EXIT (SELFX)
To exit self-refresh mode, apply minimum tCKSP after CKE brought high, and then the No Operation command (NOP) or the Deselect command (DESL) should be asserted within one tRC period. CKE should be held High within one tRC period after tCKSP Refer to "16. SELF-REFRESH ENTRY AND EXIT TIMING" in section "TIMING . DIAGRAMS" for the detail. It is recommended to assert an Auto-refresh command just after the tRC period to avoid the violation of refresh period. Note : When the burst refresh method is used, a total of 8,192 auto-refresh commands within 2 ms must be asserted after the self-refresh exit.
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MB81ES653225-12/-12L
18. MODE REGISTER SET (MRS)
The mode register of SDR I/F FCRAM provides a variety of different operations. The register consists of five operation fields; Burst Length, Burst Type, CAS latency, Operation Code and Page length. Refer to "MODE REGISTER TABLE". The mode register can be programmed by the Mode Register Set command (MRS) . Once a mode register is programmed, the contents of the register will be held until re-programmed by another MRS command. MRS command should only be issued on condition that all DQ is in Hi-Z. The condition of the mode register is undefined after the power-up stage. It is required to set each field after initialization of SDR I/F FCRAM. Refer to "22. POWER-UP INITIALIZATION".
19. EXTENDED MODE REGISTER SET (EMRS)
The extended mode register consists of two operation fields; Partial Array Self Refresh (PASR) and Temperature Compensated Self Refresh (TCSR) . Refer to "MODE REGISTER TABLE". The condition of the extended mode register is undefined after the Power-up stage. It is required to set each field after initialization of SDR I/F FCRAM. Refer to "22. POWER-UP INITIALIZATION".
20. PARTIAL ARRAY SELF REFRESH (PASR)
Memory array size to be refreshed during self refresh operation is programmable in order to reduce self refresh current. Data outside the defined area will not be retained during self refresh.
21. TEMPERATURE COMPENSATED SELF REFRESH (TCSR)
Programmable refresh rate for self refresh mode allows the system to control power as a function of temperature.
22. POWER-UP INITIALIZATION
The SDR I/F FCRAM internal condition after power-up will be undefined. It is required to follow the following Power On Sequence to execute read or write operation. 1. Apply power (VDD should be applied before or in parallel with VDDQ) and start clock. Attempt to maintain either NOP or DESL command at the input. 2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 s. 3. Precharge all banks by Precharge (PRE) or Precharge All command (PALL) . 4. Assert minimum of 2 Auto-refresh command (REF) . 5. Program the mode register by Mode Register Set command (MRS) . 6. Program the extended mode register by Extended Mode Register Set command (EMRS) . In addition, it is recommended DQM and CKE track VDD to insure that output is High-Z state. The Mode Register Set command (MRS) and Extended Mode Register Set command (EMRS) can be set before 2 Auto-refresh command (REF) .
23. DISABLE MODE
When DSE is applied high level, SDR I/F FCRAM entries Disable mode. Disable mode entry doesn't require clock. In Disable mode, SDR I/F FCRAM current consumption is less than IDD2PS and the output is High-Z. Any command isn't accepted in this mode. To exit Disable mode, apply Low level to DSE.
24. SELF BURNIN MODE
When BME is applied High level, SDR I/F FCRAM entries Self Burnin mode. Self Burnin mode entry doesn't require clock. In SELF BURNIN mode, self refresh command is asserted internally. Any command isn't accepted in this mode. To exit Self Burnin mode, apply Low level to BME.
18
MB81ES653225-12/-12L
25. BIST MODE
When TBST is applied High level, SDR I/F FCRAM entries BIST mode. BIST mode entry dosen't require clock. To exit BIST mode, apply Low level to TBST.
19
MB81ES653225-12/-12L
STATE DIAGRAM
MODE REGISTER SET
MRS
SELF
IDLE
EMRS
SELFX
SELF REFRESH
REF CKE\ (PD) ACTV CKE
EXTENDED MODE REGISTER SET
CKE(DPDX)
CKE\ (DPD)
AUTO REFRESH POWER DOWN
DEEP POWER DOWN
BANK ACTIVE SUSPEND
CKE\ (CSUS) CKE BST
BANK ACTIVE
BST
WRIT CKE\ (CSUS)
WRIT WRITA READA READ WRIT READA
READ
READ CKE\ (CSUS)
WRITE SUSPEND
CKE
WRITE
READ
CKE
READ SUSPEND
WRITA CKE\ (CSUS)
WRITA
READA
PRE or PALL
WRITE SUSPEND
CKE
WRITE WITH AUTO PRECHARGE
READ WITH AUTO PRECHARGE
PRE or PALL
CKE\ (CSUS) CKE
READ SUSPEND
PRE or PALL
POWER ON
PRE or PALL
PRECHARGE
POWER APPLIED
DEFINITION OF ALLOWS Manual Input Automatic Sequence
Note : CKE\ means CKE goes Low-level from High-level. 20
MB81ES653225-12/-12L
BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR 1 BANK OPERATION Second command (same *4 *4 bank) MRS ACTV READ READA WRIT WRITA PRE First command MRS ACTV READ tRSC *1, *2 BL + tRP *2 BL-1 + tDAL *2, *3 tRP *3 tRP tRC tRC tRSC BL + tRP BL-1 + tDAL tRP tRP tRC tRC tRCD 1 tWR tRCD 1 tWR tRCD *5 1 1 tRCD *5 1 1 tRSC tRAS *4 1 *4 BL + tRP *4 tDPL *4 BL-1 + tDAL 1 1 tRC tRC
PALL
REF
SELF
BST
tRSC tRAS *4 1 *4 BL + tRP *4 tDPL *4 BL-1 + tDAL *4 1 1 tRC tRC
tRSC *2 BL + tRP *2 BL-1 + tDAL *2 tRP tRP tRC tRC
tRSC *2, *7 BL + tRP *2 BL-1 + tDAL *2, *6 tRP *6 tRP tRC tRC
tRSC 1 1 1 1 1 tRC tRC
READA
WRIT
WRITA
PRE PALL REF SELFX : Illegal Command
*1 : If tRP (Min) < CL x tCK, minimum latency is a sum of (BL + CL) x tCK. *2 : Assume all banks are in Idle state. *3 : Assume output is in High-Z state. *4 : Assume tRAS (Min) is satisfied. *5 : Assume no I/O conflict. *6 : Assume after the last data have been appeared on DQ. *7 : If tRP (Min) < (CL - 1) x tCK, minimum latency is a sum of (BL + CL - 1) x tCK.
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MB81ES653225-12/-12L
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION Second command (other *5,*6 *5 *5, *6 *5 bank) MRS ACTV READ READA WRIT WRITA PRE PALL First command MRS ACTV READ tRSC *1, *2 BL + tRP *2 BL-1 + tDAL *2, *3 tRP *3 tRP tRC tRC tRSC * tRRD *2, *4 1 *2, *4 1 *2, *4 1 *2, *4 1 *2, *4 1 tRP tRC tRC
2
REF
SELF
BST
* 1 1 *6 1 1 *6 1 *7 1
7
* 1 1 *6 1 1 *6 1 *7 1
7
* 1
7
* 1
7
tRSC ** 1 *6 1 *6 1 *6 1 *6 1 *6, *7 1 1 tRC tRC
6, 7
tRSC * tRAS *6 1 *6 BL + tRP *6 tDPL
7
tRSC *2 BL + tRP
tRSC *2, *9 BL + tRP
tRSC 1 1 1 1 1 tRC tRC
*10 1 *6, *10 1 1 *6 1 *7 1
*10 1 *6, *10 1 1 *6 1 *7 1
READA
WRIT
WRITA
*2 *2 *6 BL-1 BL-1 BL-1 + tDAL + tDAL + tDAL *7 1 1 tRC tRC *2 tRP tRP tRC tRC *2, *8 tRP *8 tRP tRC tRC
PRE PALL REF SELFX : Illegal Command *1 *2 *3 *4 *5 *6 *7 *8 *9
: If tRP (Min) < CL x tCK, minimum latency is a sum of (BL + CL) x tCK. : Assume bank of the object is in Idle state. : Assume output is in High-Z state. : tRRD (Min) of other bank (second command will be asserted) is satisfied. : Assume other bank is in active, read or write state. : Assume tRAS (Min) is satisfied. : Assume other banks are not in READA/WRITA state. : Assume after the last data have been appeared on DQ. : If tRP (Min) < (CL - 1) x tCK, minimum latency is a sum of (BL + CL - 1) x tCK.
*10 : Assume no I/O conflict.
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MB81ES653225-12/-12L
MODE REGISTER TABLE
MODE REGISTER SET BA A14*5 A13*4 A12 A11 A10 0 PL 0 0 A9 Opcode A8*3 A7*3 0 0 A6 A5 CL A4 A3 BT A2 A1 BL A0 ADDRESS MODE REGISTER Burst Length BT = 0 1 2 4 8 Reserved Reserved Reserved Full Column Burst Type Sequential (Wrap round, Binary-up) Interleave (Wrap round, Binary-up) BT = 1*2 Reserved 2 4 8 Reserved Reserved Reserved Reserved
A14
A13
A12 1 0 1 0 1 0 1
PAGE LENGTH 128 page 64 page Reserved 32 page Reserved Reserved Reserved
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 CAS Latency 0 1 0 1 0 1 0 1 Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
GND GND GND GND 1 1 1 1 1 1 0 0 1 1
A9 0 1
Op-code
A3 0
*1
Burst Read & Burst Write Burst Read & Single Write
1
EXTENDED MODE REGISTER BA A14*5 A13*4 A12 A11 1 0 0 0 0 A10 0 A9 0 A8 0 A7 0 A6 0 A5 0 A4 A3 A2 A1 PASR A0 ADDRESS EXTENDED MODE REGISTER
TCSR
A4 0 0 1 1
A3 0 1 0 1
MAX TEMPERATURE (Ta) *6 + 70 C + 45 C + 15 C + 85 C
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
SELF REFRESH AREA 64 M bit 32 M bit (RA11 = 0) 16 M bit (RA11 = RA10 = 0) Reserved Reserved Reserved Reserved Reserved
*1. When A9 = 1, burst length at Write is always one regardless of BL value. *2. BL = 1 and Full column are not applicable to the interleave mode. *3. A7 = 1 and A8 = 1 are reserved for vender test. *4. A13 exists at operation with 32 and 64 page length mode. *5. A14 exists at operation with 32 page length mode. *6. Ta is ambient temperature. 23
MB81ES653225-12/-12L
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Storage Temperature Symbol VDD, VDDQ VIN, VOUT IOUT PD TSTG Rating Min - 0.5 - 0.5 - 50 - 55 Max + 3.0 + 3.0 + 50 1.0 + 125 Unit V V mA W C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage *1 Input Low Voltage *2 Ambient Temperature Junction Temperature *3 MB81ES653225-12 MB81ES653225-12L MB81ES653225-12 MB81ES653225-12L Symbol VDD, VDDQ VSS, VSSQ VIH VIL Ta Tj Min 1.65 0 VDDQ x 0.8 -0 .3 0 - 25 0 - 25
VIH
Value Typ 1.8 0
Max 1.95 0 VDDQ + 0.3 VDDQ x 0.2 + 85 + 85 + 100 + 100
Unit V V V V C C C C
3.0 V
Pulse width 5 ns
VIH VIH Min VIL
50% of pulse amplitude
VIL Max VIL -1.0 V
50% of pulse amplitude
Pulse width 5 ns
*1 : Overshoot limit : VIH (Max) = 3.0 V for pulse width 5 ns, pulse width measured at 50% of pulse amplitude.
*2 : Undershoot limit : VIL (Min) = VSSQ - 1.0 V for pulse width 5 ns, pulse width measured at 50% of pulse amplitude.
*3 : The maximum junction temperature of FCRAM (Tj) should not be more than 100 C. Tj is represented by the power consumption of FCRAM (PFCRAM) and Logic LSI (PD) , the thermal resistance of the package ( ja) , and the maximum ambient temperature of the SiP (Tamax) . pmax[W] = PFCRAM + PD Tjmax[ C] = Tamax[ C] + ja[ C/W] x pmax[W] WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 24
MB81ES653225-12/-12L
CAPACITANCE
(Ta = +25 C, f = 1 MHz) Parameter Input Capacitance, Except for CLK Input Capacitance for CLK I/O Capacitance Symbol CIN1 CIN2 CI/O Min 1.5 1.5 2.0 Typ Max 3.0 3.0 4.0 Unit pF pF pF
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MB81ES653225-12/-12L
DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) *1, *2, *3 Parameter Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Symbol VOH (DC) IOH = -0.1 mA VOL (DC) IOL = 0.1 mA ILI ILO 0 V VIN VDDQ; All other pins not under test = 0 V 0 V VIN VDDQ; Data out disabled Burst Length = 1 tRC = Min, tCK = Min One bank active Operating Current (Average Power Supply Current) IDD1 Output pin open Address changed up to 1 time during tRC (Min) 0 V VIN VIL Max VIH Min VIN VDD -12 IDD2P -12L CKE = VIL All banks idle tCK = Min Power down mode 0 V VIN VIL Max VIH Min VIN VDD CKE = VIL All banks idle CLK = VIH or VIL Power down mode 0 V VIN VIL Max VIH Min VIN VDD CKE = VIH All banks idle, tCK = 20 ns NOP commands only, Input signals (except for CMD) are changed 1 time during 2 clocks. 0 V VIN VIL Max VIH Min VIN VDD CKE = VIH All banks idle CLK = VIH or VIL Input signal are stable. 0 V VIN VIL Max VIH Min VIN VDD 128 page length Condition Value Min VDDQ - 0.2 -5 -5 Max 0.2 5 5 Unit V V A A
50
64 page length
40
mA
32 page length
35
1 mA
0.4
-12 IDD2PS -12L Precharge Standby Current (Power Supply Current) IDD2N
0.5 mA
0.1
8
mA
IDD2NS
1
mA
(Continued)
26
MB81ES653225-12/-12L
(At recommended operating conditions unless otherwise noted.) *1, *2, *3 Parameter Symbol CKE = VIL Any bank active tCK = Min 0 V VIN VIL Max VIH Min VIN VDD CKE = VIL Any bank active CLK = VIH or VIL 0 V VIN VIL Max VIH Min VIN VDD CKE = VIH Any bank active tCK = 20 ns NOP commands only, Input signals (except for CMD) are changed 1 time during 2 clocks. 0 V VIN VIL Max VIH Min VIN VDD CKE = VIH Any bank active CLK = VIH or VIL Input signals are stable. 0 V VIN VIL Max VIH Min VIN VDD tCK = Min Burst Length = 4 Output pin open All-banks active Gapless data 0 V VIN VIL Max VIH Min VIN VDD Auto-refresh; tCK = Min tRC = Min 0 V VIN VIL Max VIH Min VIN VDD Condition Value Min Max 1 mA 0.7 Unit
-12 IDD3P -12L
-12 IDD3PS -12L Active Standby Current (Power Supply Current) IDD3N
0.7 mA
0.5
14
mA
IDD3NS
1
mA
Burst mode Current (Average Power Supply Current)
IDD4
68
mA
Refresh Current#1 (Average Power Supply Current)
IDD5
50
mA
(Continued)
27
MB81ES653225-12/-12L
(Continued) (At recommended operating conditions unless otherwise noted.) *1, *2, *3 Parameter -12 -12L -12 -12L -12 -12L -12 -12L -12 -12L Refresh Current #2 *4 (Average Power Supply Current) -12 -12L -12 -12L -12 -12L -12 -12L -12 -12L -12 -12L -12 -12L Precharge Standby Current in Deep Power Down mode -12 IDD7 -12L CKE 0.2 V All banks idle Deep Power Down mode 0 V VIN VIL Max VIH Min VIN VDD IDD6 Self-refresh; tCK = Min CKE 0.2 V 0 V VIN VIL Max VIH Min VIN VDDQ Symbol Condition PASR = "000" (64 Mbit) TCSR = "00" PASR = "001" (Ta +70 C) (32 Mbit) PASR = "010" (16 Mbit) PASR = "000" (64 Mbit) TCSR = "01" PASR = "001" (Ta +45 C) (32 Mbit) PASR = "010" (16 Mbit) PASR = "000" (64 Mbit) TCSR = "10" PASR = "001" (Ta +15 C) (32 Mbit) PASR = "010" (16 Mbit) PASR = "000" (64 Mbit) TCSR = "11" PASR = "001" (Ta +85 C) (32 Mbit) PASR = "010" (16 Mbit) Value Min Max 760 285 640 200 580 155 640 200 580 150 550 130 560 130 540 115 530 105 1000 450 760 290 640 205 50 A 10 A Unit
*1 : All voltages are referenced to VSS. *2 : DC characteristics are measured after following the "22. POWER-UP INITIALIZATION" procedure in section "FUNCTIONAL DESCRIPTION." *3 : IDD depends on the output termination or load condition, clock cycle rate, signal clocking rate. The specified values are obtained with the output open and no termination resistor. *4 : The measurement conditions of IDD6 is assumed below. Total power of devices in package ( pmax) = 0.75 W The thermal resistance of the package ( ja) = 20 C/W 28
MB81ES653225-12/-12L
AC CHARACTERISTICS
1. BASIC AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) *1, *2, *3 Parameter Clock Period Clock High Time *5 Clock Low Time *5 Input Setup Time * Input Hold Time *
5 5
Symbol CL = 2 CL = 3 tCK2 tCK3 tCH tCL tSI tHI CL = 2 CL = 3 -12 -12L -12 -12L -12 -12L tAC2 tAC3 tLZ CL = 2 tHZ2 tHZ3 tOH tREFI tREF tT tCKSP
Value Min 18.5 11.7 tCK x 0.3 tCK x 0.3 2.5 1 0 2 1.5 2 1.5 2 1.5 0.5 2.5 Max 12 8.7 12 8.7 3.9 32 10
Unit ns ns ns ns ns ns ns ns ns ns ns ns s ms ns ns
Access Time from Clock (TCK = Min) *5, *6, *7 Output in Low-Z *
5
Output in High-Z *5, *7, *8 CL = 3 Output Hold Time *4 Time between Auto-Refresh command interval Time between Refresh Transition Time CKE Setup Time for Power Down Exit Time *5
*1 : AC characteristics are measured after following the "22. POWER-UP INITIALIZATION" procedure in section "FUNCTIONAL DESCRIPTION". *2 : AC characteristics assume tT = 1 ns, 10 pF of capacitive load and 50 of terminated load. Refer to "5. MEASUREMENT CONDITION OF THE AC CHARACTERISTICS". *3 : 0.9 V is the reference level for 1.8 V I/O for measuring timing of input/output signals. Transition times are measured between VIH (Min) and VIL (Max) . *4 : This value is for reference only. *5 : If input signal transition time (tT) is longer than 1 ns; [ (tT/2) - 0.5] ns should be added to tAC (Max) , tHZ (Max) , and tCKSP (Min) spec values, [ (tT/2) - 0.5] ns should be subtracted from tLZ (Min) , tHZ (Min) , and tOH (Min) spec values, and (tT - 1.0) ns should be added to tCH (Min) , tCL (Min) , tSI (Min) , and tHI (Min) spec values. *6 : tAC also specifies the access time at burst mode. *7 : tAC and tOH are measured under output load circuit shown in "5. MEASUREMENT CONDITION OF THE AC CHARACTERISTICS". *8 : Specified where output buffer is no longer driven.
29
MB81ES653225-12/-12L
2. BASE VALUES FOR CLOCK COUNT/LATENCY
Parameter RAS Cycle Time * RAS Precharge Time RAS Active Time RAS to CAS Delay Time Write Recovery Time RAS to RAS Bank Active Delay Time Data-in to Precharge Lead Time CL = 2 Data-in to Active/Refresh Command Period CL = 3 -12 -12L -12 -12L Symbol tRC tRP tRAS tRCD tWR tRRD tDPL tDAL2 tDAL3 tRSC Value Min 80 20 60 20 11.7 20 18.5/20 1 cyc + tRP 2 cyc + tRP 2 cyc + tRP 2 cyc + tRP 20 Max 110000 Unit ns ns ns ns ns ns ns ns ns ns
Mode Register Set Cycle Time
* : Actual clock count of tRC (lRC) will be sum of clock count of tRAS (lRAS) and tRP (lRP) .
3. CLOCK COUNT FORMULA
Clock Base Value Clock Period (Round up a whole number)
Note : All base values are measured from the clock edge at the command input to the clock edge for the next command input. All clock counts are calculated by a simple formula : clock count equals base value divided by clock period (round off to a whole number) .
4. LATENCY (The latency values on these parameters are fixed regardless of clock period.)
Parameter CKE to Clock Disable DQM to Output in High-Z DQM to Input Data Delay Last Output to Write Command Delay Write Command to Input Data Delay Precharge to Output in High-Z Delay Burst Stop Command to Output in High-Z Delay CAS to CAS Delay (Min) CAS Bank Delay (Min) 30 CL = 2 CL = 3 CL = 2 CL = 3 Symbol MB81ES653225-12 MB81ES653225-12L lCKE lDQZ lDQD lOWD lDWD lROH2 lROH3 lBSH2 lBSH3 lCCD lCBD 1 2 0 2 0 2 3 2 3 1 1 1 2 0 2 0 2 3 2 3 1 1 Unit cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
MB81ES653225-12/-12L
5. MEASUREMENT CONDITION OF AC CHARACTERISTICS
R1 = 50 Output 0.9 V
CL = 10 pF
6. SETUP, HOLD AND DELAY TIME
tCK
1.44 V
tCH
tCL
CLK
0.9 V 0.36 V
tSI
tHI 1.44 V 0.9 V 0.36 V tHZ tOH
Iutput (Control, Addr. & Data)
tAC tLZ
Output
0.9 V
Note : Reference level of input signal is 0.9 V for LVCMOS. Access time is measured at 0.9 V for LVCMOS. AC characteristics are also measured in this condition.
31
MB81ES653225-12/-12L
7. DELAY TIME FOR POWER DOWN EXIT
CLK
H or L tCKSP (Min) 1 clock (Min)
CKE
Command
H or L
NOP
NOP
ACTV
8. PULSE WIDTH
CLK
tRC, tRP, tRAS, tRCD, tWR, tREF,
Input (Control)
tDPL, tDAL, tRSC, tRRD, tCKSP COMMAND COMMAND
Note : These parameters are a limit value of the rising edge of the clock from one command input to next input. tCKSP is the latency value from the rising edge of CKE. Measurement reference voltage is 0.9 V.
32
MB81ES653225-12/-12L
9. ACCESS TIME
CLK
Command
READ
tAC (CAS Latency - 1) x tCK
tAC
tAC
DQ31 to DQ0 (Output)
Q (Valid)
Q (Valid)
Q (Valid)
33
MB81ES653225-12/-12L
TIMING DIAGRAMS
1. CLOCK ENABLE-READ AND WRITE SUSPEND (@ BL = 4)
CLK
CKE
ICKE 1 (1 clock) lCKE 1 (1 clock)
CLK (Internal)
DQ31 to DQ0 (Read)
Q1
Q2
(NO CHANGE)
2
Q3
2 (NO CHANGE)
Q4
DQ31 to DQ0 (Write)
D1
NOT 3 WRITTEN
D2
NOT 3 WRITTEN
D3
D4
*1 : The latency of CKE (lCKE) is one clock. *2 : During read mode, burst counter will not be incremented/decremented at the next clock of CSUS command. Output data remain the same data. *3 : During the write mode, data at the next clock of CSUS command is ignored.
2. POWER DOWN ENTRY AND EXIT
CLK
tCKSP (Min) 1clock (Min)
CKE
Command
1 NOP
PD (NOP)2
H or L tREF (Max)
PDX
NOP
3
ACTV
4
*1 : Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode. *2 : Precharge command can be posted in conjunction with CKE after the last read data have been appeared on DQ. *3 : It is recommended to apply NOP command in conjunction with CKE. *4 : The ACTV command can be latched after tCKSP (Min) + 1 clock (Min) .
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MB81ES653225-12/-12L
3. COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
RAS
tRCD (Min)
ICCD (1 clock)
ICCD
ICCD
ICCD
CAS
Address
ROW ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
COLUMN ADDRESS
Note : CAS to CAS delay (lCCD) can be one or more clock period.
4. DIFFERENT BANK ADDRESS INPUT DELAY
CLK
tRRD (Min)
RAS
tRCD (Min)
ICBD (1 clock)
ICBD (1 clock)
CAS
tRCD(Min) ROW ADDRESS ROW ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS
Address
BA
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Note : CAS Bank delay (lCBD) can be one or more clock period.
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MB81ES653225-12/-12L
5. INPUT MASK AND OUTPUT DISABLE (@ BL = 4)
CLK
DQM3 to DQM0 (@ Read)
IDQZ (2 clocks)
DQ31 to DQ0 (@ Read)
Q1
Q2
Hi-Z
Q4
End of burst
DQM3 to DQM0 (@ Write)
IDQD (same clock)
DQ31 to DQ0 (@ Write)
D1
MASKED
D3
D4
End of burst
6. PRECHARGE TIMING (APPLIED TO THE SAME BANK)
CLK
tRAS (Min) PRE
Command
ACTV
* : PRE means 'PRE' or 'PALL'.
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MB81ES653225-12/-12L
7. READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 4)
CLK
Command
PRE2 IROH (2 clocks) *1
DQ31 to DQ0
Hi-Z Q1
Command
PRE2 IROH (2 clocks) *1 Hi-Z Q1 Q2
DQ31 to DQ0
Command
PRE2 IROH (2 clocks) *1
DQ31 to DQ0
Hi-Z Q1 Q2 Q3
Command
PRE2 No effect (end of burst)
DQ31 to DQ0
Q1
Q2
Q3
Q4
Hi-Z
*1 : In case of CL = 2, the lROH2 is 2 clocks. *2 : PRE means 'PRE' or 'PALL'.
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MB81ES653225-12/-12L
8. READ INTERRUPTED BY BURST STOP (EXAMPLE @CL = 2, BL = Full Column)
CLK
Command
BST IBSH (2 clocks)
Hi-Z
DQ31 to DQ0
Qn - 2
Qn - 1
Qn
Qn + 1
9. WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ BL = 2)
CLK
Command
BST
COMMAND
DQ31 to DQ0
LAST DATA-IN
Masked by BST
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MB81ES653225-12/-12L
10. WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2)
CLK
Command
tDPL (Min)
PRE tRP (Min)
ACTV
DQ31 to DQ0
DATA-IN
LAST DATA-IN
MASKED by Precharge
Note : The precharge command (PRE) should only be issued after the tDPL of final data input is satisfied. PRE means 'PRE' or 'PALL'.
11. READ INTERRUPTED BY WRITE (EXAMPLE @ CL = 2, BL = 4)
CLK
IOWD (2 clocks)
Command
READ
WRIT
DQM3 to DQM0
1
2 IDQZ (2 clocks)
3 IDWD (same clock)
DQ31 to DQ0
Q1
Masked
D1
D2
*1 : First DQM makes high-impedance state High-Z between last output and first input data. *2 : Second DQM makes internal output data mask to avoid bus contention. *3 : Third DQM also makes internal output data mask. If burst read ends (final data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus contention.
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MB81ES653225-12/-12L
12. WRITE TO READ TIMING (EXAMPLE @ CL = 2, BL = 4)
CLK
tWR (Min)
Command
WRIT
READ
DQM3 to DQM0
(CL - 1) x tCK
tAC (Max) Q1 Q2 Q3
DQ31 to DQ0
D1
D2
D3 Masked by READ
Note : Read command should be issued after tWR of final data input is satisfied.
13. READ WITH AUTO-PRECHARGE (EXAPLE @ CL = 2, BL = 2, Applied to same bank)
tRAS (Min)
CLK
tRP (Min) READA2 2 clocks *1 (same value as BL)
Command
ACTV
NOP
ACTV
DQM3 to DQM0
DQ31 to DQ0
Q1
Q2
*1 : Precharge at read with Auto-precharge command (READA) is started from number of clocks that is the same as Burst Length (BL) after the READA command is asserted. *2 : Next ACTV command should be issued after BL + tRP (min) from READA command.
40
MB81ES653225-12/-12L
14. WRITE WITH AUTO-PRECHARGE (EXAMPLE @ CL = 2, BL = 2, Applied to same bank) *1, *2, *3
tRAS (Min)
CLK
1 clock *4 tDAL (Min) BL + tRP (Min) *5
Command
ACTV
WRITA
NOP
ACTV
DQM3 to DQM0
DQ31 to DQ0
D1
D2
*1 : Even if the final data is masked by DQM, the precharge does not start the clock of final data input. *2 : Once auto precharge command is asserted, no new command within the same bank can be issued. *3 : Auto-precharge command doesn't affect at full column burst operation except Burst READ & Single Write. *4 : Precharge at write with Auto-precharge is started after 1 clock at CL = 2 (-12) , 2 clock at CL = 2 (-12L) and CL = 3 from the end of burst. *5 : Next command should be issued after BL + tRP (min) at CL = 2 (-12) , BL + 1 + tRP (min) at CL = 2 (-12L) and CL = 3 from WRITA command.
15. AUTO-REFRESH TIMING
CLK
Command
REF 1
NOP 3 tRC (Min)
REF
NOP 3 tRC (Min)
COMMAND 4
BA
H or L 2
H or L 2
BA
*1 : All banks should be precharged prior to the first Auto-refresh command (REF) . *2 : Bank select is ignored at REF command. The refresh address and bank select are selected by internal refresh counter. *3 : Either NOP or DESL command should be asserted during tRC period while Auto-refresh mode. *4 : Any activation command such as ACTV or MRS command other than REF command should be asserted after tRC from the last REF command. 41
MB81ES653225-12/-12L
16. SELF-REFRESH ENTRY AND EXIT TIMING
CLK
tSI (Min) tCKSP (Min)
CKE
5 tRC (Min) *4
Command
H or L
NOP 1
SELF
H or L
NOP 2
SELFX
NOP 3
COMMAND
*1 : Precharge command (PRE or PALL) should be asserted if any bank is active prior to Self-refresh Entry command (SELF) . *2 : The Self-refresh Exit command (SELFX) is latched after tCKSP (Min) . It is recommended to apply NOP command in conjunction with CKE. *3 : Either NOP or DESL command can be used during tRC period. *4 : CKE should be held high within one tRC period after tCKSP. *5 : CKE level should be held less than 0.2 V during self-refresh mode.
17. MODE REGISTER SET TIMING
CLK
tRSC (Min)
Command
MRS
NOP
ACTV
Address
MODE
ROW ADDRESS
Note : The Mode Register Set command (MRS) should only be asserted after all banks have been precharged.
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MB81ES653225-12/-12L
18. DEEP POWER DOWN ENTRY TIMING
CLK
tSI (Min)
CKE
Command
H or L
NOP
DPD
H or L
Note : Deep Power Down Command (DPD) should only be asserted if all banks have been precharged and all outputs are in High-Z.
19. DEEP POWER DOWN EXIT TIMING
CLK
tCKSP (Min)
CKE
200 s (Min) tRP (Min) tRC (Min) tRC (Min) tRSC tRSC (Min) (Min)
Command
H or L
NOP DPDX
NOP
PALL REF
REF
MRS EMRS ACVT
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MB81ES653225-12/-12L
FUJITSU LIMITED
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F0412 (c) 2004 FUJITSU LIMITED Printed in Japan

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